1. Field of the Invention
The present invention generally relates to an slew-rate control circuitry, and particularly to a slew-rate control circuitry consists of output buffer and feedback.
2. Description of the Related Art
For a good design of an integrate circuit (IC), output driver is one of the essential component which will determine IC's overall performance especially on the field of data and telecommunication system since they are often required to comply with specified interface. As an example, the output driver for RS232 serial interface standard must support the driving of a resistive load of about 3-7 k ohms with a voltage swing greater than ±5 volts and the driving of a capacitive load of about 2500 pF at a frequency of 250 Kbps since the load for RS232 is ohmic-capative type. Therefore it is very important to have precise control of the slew rate of the output driver so that the edge transitions of the output signal can be maintained within acceptable range and additionally ensure an accurate control of the output waveform as the load connected to the output driver varies which will often affect data transmission rate. For an ideal design of the RS232 output buffer, the slew rate must be kept under 30 volts/usec in order to minimize undesirable high frequency components of the output signal which may cause high electromagnetic interference (EMI) due to high output edge switching rates.
Since the output buffers for IC has so many constraints due to the above-mentioned requirements, traditional design of output buffers is being limited by DC operating characteristics which affect the sizing of output transistor. As a result, high current peaks will occur with the simultaneous switching of output buffers and the inductive power supply noise will create high voltage drop. FIG. 1 is a circuit for a traditional output buffer with slew-rate control, the pre-driver 2 is connected to a P-channel Metal Oxide Semiconductor (PMOS) 4 and a N-channel Metal Oxide Semiconductor (NMOS) 6. The pre-driver 2 further connected to a supply voltage VDD of 2.5 volts in one end and VSS of 0 volts at another end. The outcome of this circuit provides a switching voltage with push-pull configuration to the I/O pad 8. The output voltage from I/O pad 8 is then connected to a resistor 10 for ESD protection, a input inverter 14 and another NMOS 12 for CDM ESD protection before going to the internal circuit. The disadvantage with such design is that when the input signal has greater voltage than the VDD, leakage current is likely to occur at the output of PMOS 4 and parasitic drain-to-well junction diode section 16 due to the large biased voltage. In addition, there will also be gate-oxide reliability concern at the output of NMOS 6, gate-grounded NMOS 12 and input inverter 14 since they are exposed outside of the IC.
Based upon the foregoing, the aim of the present invention is to provide a slew-rate control circuit with better output buffer performance and gate-tracking ability without the requirement of using external component. The output buffer of the slew-rate control circuit not only provides an IC with build-in slew-rate control and better gate-oxide reliability, but also reduces the number of MOS used externally which decreases the cost of manufacturing.